Consistency of cell arrays is a key factor for determining static performance static performance, such as Differential Nonlinearity (DNL) and Integral Nonlinearity (INL), and dynamic performance, such as a Spurious-free dynamic range (SFDR) and a Signal to Noise and Distortion Ratio (SNDR), of a DAC. Therefore, in application of a high-resolution current-steering DAC, there is a high requirement on matching accuracy of current source arrays.
However, in a practical chip manufacturing process, oxide film thickness, doping, stress and other parameters usually vary with chip positions, and usually present a linear gradient change trend. In addition, when the chip is in use, different positions in the chip have different temperatures and power supply voltage drops. These non-ideal factors cause a non-random matching error of the current source array, which affects performance like linearity and resolution of the current-steering DAC. In the layout design of the current source array, specific arrangement of current source cells and bias current mirrors may significantly reduce a first-order non-random error and a second-order non-random error caused by variation of the process, temperature and voltage.
Referring to FIG. 1, FIG. 1 schematically illustrates a diagram of a layout of a common centroid current source array in the prior art. An implementation is that current source cells are symmetrically arranged in upper, lower, left and right directions in accordance with a center position of the current source array, which suppresses the non-random errors.
Compared with the current source array in a sequential arrangement, the existing common centroid array may reduce influence of the non-random error of the current source array on the performance of the DAC, but its ability to suppress the error is weak, which is still insufficient for high performance applications.